1. Field of the Invention
The present invention relates to a microcomputer, and more specifically, a microcomputer including a interrupt controller requesting an interrupt processing to an central processing unit in response to an interrupt request signal outputted from peripheral hardware.
2. Description of Related Art
Recently, microcomputers have been used in many and different fields. Particularly, single-chip microcomputers have been widely used or incorporated in a home use field including air conditioners and electric rice cookers, and in various control instruments including robots and motor controllers, since the single-chip microcomputers are inexpensive for the reason that a central processing unit (called "CPU" hereinafter), a RAM (random access memory), a ROM (read only memory) and peripheral devices are integrated on a single chip.
As mentioned above, since the single-chip microcomputer includes the CPU and the peripheral hardware therein, the single-chip microcomputer also includes therein an interrupt controller for controlling an interrupt request from the peripheral hardware.
In general, the interrupt controller has the following functions:
(1) To receive an interrupt request from each peripheral hardware, and to request an interrupt processing to the CPU;
(2) To inform the CPU of a location storing a head address of an interrupt processing program (called a "vector code" hereinafter); and
(3) To discriminate the order of priority when a plurality of interrupt requests are generated or when a separate interrupt request is generated in the course of execution of a processing for one interrupt request, and to accept or acknowledge an interrupt request having the highest order of priority.
In the above mentioned conventional single-chip microcomputer including the interrupt controller therein, when the internal interrupt controller is tested by use of a so-called LSI tester, a test pattern is prepared in the following manner while causing the CPU to execute instructions.
(a) Determine whether or not the interrupt controller had requested an interrupt processing to the CPU in response to an interrupt request outputted from the peripheral hardware, is checked by writing specific values to an input/output interface by means of execution of an instruction in the execution course of an interrupt processing program performed as the result of acknowledgement of the interrupt processing request by the CPU, and by examining whether or not values appearing on external terminals of the single-chip microcomputer change in accordance with the interrupt processing program;
(b) Determine whether or not the priority order control is properly executed is checked by making contents of the interrupt processing programs different from one another for each interrupt request source, and monitoring which of the interrupt processing programs is executed by the CPU; and
(c) Change of a priority level hold register and changes of interrupt flags caused by an interrupt request clear signal are checked by reading the priority level hold register and the interrupt flags by means of execution of an instruction, and then writing the read data to the input/output interface by means of execution of an instruction, so that values appearing on external terminals of the single-chip microcomputer will change.
As seen from the above, in the test of the internal interrupt controller of the conventional single-chip microcomputer, since it is necessary to write data to the input/output interface so as to cause the data to be outputted from the external terminals, it is necessary to previously initialize the input/output interface so that change of the data on the external terminals can be easily discriminated or detected. Therefore, the number of test patterns inevitably becomes large.
Since several clock cycles are required after the interrupt controller outputs the interrupt processing request signal to the CPU until the CPU executes a first instruction of a requested interrupt processing program, there will inevitably exist a number of patterns independent of the internal test of the interrupt controller.
To test the speed of critical paths within the interrupt controller, it is necessary to continuously monitor the execution timing of each instruction by the CPU while increasing the execution speed. This requires a sufficiently long test pattern which is difficult, if not impossible, to prepare.
The above problems become more serious if the number of interrupt request signals generated by the peripheral hardware increases. In addition, the time for executing the test becomes long, and also, the time for preparing the test pattern becomes long. As a result, a total chip cost for microcomputers is increased.